The present invention relates to a circuit arrangement for adding and subtracting BCD coded numerical values under control of instructions contained in a memory.
Circuit arrangements in electronic data processing systems are known to include binary adder circuits for decimal processing with which numerical values, or numbers, coded according to a BCD (binary coded decimal) code can be added and subtracted. The circuit arrangement cooperating with the binary adder circuit is constructed so that for subtractions, i.e., minuend - subtrahend = difference, the unit complement of the subtrahend is added to the minuend and to a possibly present input carry from processing of the preceding decimal digit, a 1 having been stored in the carry circuit before the start of the subtraction. By interrogating the output carry it is determined whether correction of the result is necessary. If the binary output carry is 0, a 6 must be subtracted, to correct the pseudotetrade, and this is done by the addition of a 10.
For addition problems, i.e., summand + addend = sum, the BCD values are added in the binary adder under consideration of a possible carry from previously added digits, and thereafter the result is checked for pseudotetrades. If pseudotetrades are present, a binary 6 must be added and the pseudotetrades must be generated into the carry.
These known circuit arrangements comprise a considerable amount of hardware which is particularly noticeable if the circuit is to process a plurality of numbers during one passage. The amount of hardware can, of course, be reduced by employing suitable software to process a plurality of numbers or even bits, in several passages. This, however, requires a substantial amount of time which thus makes such devices unduly slow.